SystemVerilog for Verification

Education Duration :4 Days

Education Language : English 

Tranier : Nigel Woolaway

Prerequsite : -

Target Audionce : Experienced verification engineers

Content : 

This 4 days course is aimed at experienced Verification engineers who wish to learn about verification with SystemVerilog.

The course stresses a methodology for implementing these features in your verification environment.

This course is taught for all the leading simulators although not all simulators will support every feature immediately.

The course is a consistent mix of lecture and lab-exercises. Targeted quizzes and labs are designed to reinforce the course material.

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 SystemVerilog Assertions (SVA)

Education Duration : 1 Day

Education Language : English 

Tranier : Nigel Woolaway

Prerequsite : -

Target Audionce :  Design and Verification Engineers

Content : 

This one-day course is targeted at Design and Verification engineers who wish to deploy Assertion based Verification within their next project. Assertion Based Verification is becoming a cornerstone of good design and verification practice. SystemVerilog is one of the first languages to feature a 100% native temporal assertion syntax, making it extremely well integrated with the language. Our course stresses a methodical approach to learning and developing good coding style.
This course, which is taught for all the leading simulators is a consistant mix of lecture and lab-exercises. Targetted quizzes and labs are designed to reinforce the course material.
Although the content of this class overlaps the final day of our SystemVerilog for Design and SystemVerilog for Verification courses, both SVA and our course are applicable to Verilog projects with no other SystemVerilog content.

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 Introduction to Universal Verification Methodology (UVM)

Education Duration : 4 Days

Education Language : English 

Tranier : Nigel Woolaway

Prerequsite : -

Target Audionce :  System Verilog Verification Engineers

Content : 

This 4-day course is for engineers interested in developing SystemVerilog verification environments using the latest Universal Verification Methodology (UVM).
Students will first learn:

• Basic testbench structure

• How to model communication at the transaction level (TLM)

• How to write analysis components such as Scoreboards and Coverage Collectors

• Strategies for connecting to RTL designs

After mastering the basics, students will learn best-practice techniques to maximize the reusability of their test environments. Topics include:

• Using the UVM factory

• Managing complexity using hierarchy and factory overrides

• Making reusable testbenches

• Developing test cases using UVM sequences Using UVM Registers

 

 Introduction to VHDL for RTL Design

Education Duration : 4 Days

Education Language : English 

Tranier : Nigel Woolaway

Prerequsite : -

Target Audionce : Beginners to VHDL Design

Content :

A 4 days course teaching designer to write efficient, accurate RTL code for synthesis as well as basic testbenching and verification techniques.

This course is intended for designers who are new to VHDL. It focuses on teaching good RTL coding style for synthesis but also discusses basic testbenching and verification techniques.
This course continuously mixes lecture and exercise. There is a simulation exercise for most topics providing a very hands-on experience.

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 Advanced VHDL

Education Duration : 3 Days

Education Language : English 

Tranier : Nigel Woolaway

Prerequsite : “Introduction to VHDL for RTL Design”

Target Audionce : Experienced VHDL Designers

Content :

A 3 days course emphasizing behavioral techniques, testbench strategies and design management.
The 3-day Advanced VHDL class is aimed at experienced VHDL users who wish to take their use of the language to a higher level. The course is a consistant mix of lecture and lab-exercises.
A pre-requisite for this course is the Introduction to VHDL course or equivalent experience.